Chipmakers rely on patterned wafer inspection, defect classification and review, metrology, and statistical analysis to design fabrication recipes and ensure that processes and tools adhere to process window parameters throughout the fabrication process. Data is gathered and used extensively and, as process technologies become more complex, massive data gathering, statistical techniques, and machine learning are used to improve recipes and chip performance and yield.
Patterned wafer inspection scans wafers at high speed to identify potential particles, pattern flaws, and other conditions that may compromise the functionality and performance of completed die. E-beam review enables potential defects to be visualized and characterized. Data obtained from metrology ensures that devices and structures maintain precise physical dimensions and electrical properties.
Applied’s inspection, review, and metrology technologies help enable today’s most challenging materials and device engineering which in turn make accurate and complete measurement and imaging more difficult. These technologies include optical proximity correction mask qualification and self-aligned double and quadruple patterning. Advanced algorithms and machine learning are used together with leading-edge optical and e-beam technologies to enhance data generation and help accelerate access to actionable information, enabling chipmakers to shorten time to market and optimize yields in high-volume production.