Raider® GT ECD
As feature sizes continue to scale down to less than 10nm and aspect ratios increase (>5:1), the industry is being challenged to achieve the balance of bottom-up fill and sidewall suppression that produces flawless fill. In addition, thinner seed layers, with increased resistance, and higher device densities make it more difficult to obtain uniform deposition across the wafer to achieve high device yields. Upper-level metal stacks are requiring alternative metallization techniques, for example using cobalt rather than copper.
The Raider GT ECD system for copper interconnect gap fill in memory and logic devices features dynamic current-control technology, microsecond recipe control, and the ability to use the widest range of process chemistry (low to high bath conductivity). These features are key to its optimal small feature filling capability and deposition uniformity across the wafer. The ability of the system to dynamically and rapidly adjust and control the current density as the wafer enters solution and throughout deposition is the core of the Raider GT technology.
GT system extendability is enabling sub-20nm small-feature fill with high productivity and low cost of ownership. Uniquely flexible, the Raider GT design allows for a portion of the system to run a second chemistry. Both chemistries can be run simultaneously or the configuration can be changed, with minimal downtime, to allow a single chemical process to be run for maximum productivity.