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Centura® Integrated Gate Stack

高 k 栅介质/金属栅极晶体管中,介电质叠层由氧化物界面层和本体高 k 栅介质层组成。

Centura Integrated Gate Stack 系统介绍

接近每个节点时,必须缩减叠层厚度以满足不断降低的等效氧化层厚度 (EOT) 目标,从而达到期望的器件性能。微缩至 22nm 及以下时,需要采用原子层沉积 (ALD) 技术才能获得超薄的高 k 介电层。为进一步缩减等效氧化层厚度 (EOT),需要利用等离子氮化工艺,通过控制将一定剂量的氮加入叠层中,接着进行退火,以稳定加入的氮原子。

此系统包含一个原子层沉积 HfO{0}(氧化铪)沉积腔室及用于界面层氧化物形成、后期高 k 栅介质氮化和氮化后退火的专用腔室。

Integrating these chambers on a single cluster tool is essential for fabricating high-performance transistors at the 22nm and 14nm nodes. The dielectric gate stack is the core of the transistor and is electrically very sensitive to variation and quality. At each logic technology node reduction, the interface-to-bulk ratio increases dramatically, making elimination of queue time ever more crucial to avoid thickening of the interface layers. Also, during air breaks, molecular contaminants (e.g., C, N, O, F, S) can be incorporated into the gate stack interfaces. Integrating the process chambers onto a single vacuum mainframe is the surest way of minimizing these issues and ensuring repeatable, high-quality performance.