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Thick Epitaxial Silicon Enhances Perfomance of Power and MEMS Devices

Mike Rosa, PhD

Power semiconductors and MEMS-based sensors and actuators are fundamental to the advanced capabilities and effective power management of mobile products and advanced systems. One way to enhance the performance of these power and MEMS devices is by using thicker epitaxial (epi) layers, an approach that is gaining traction for a range of applications.

“Thick” is a relative term, of course. Today, epi films of more than 20μm are regarded as thick, although developmental targets for epi films can be as much as ~150μm in thickness.

For power semiconductors it’s the electrical isolating qualities of the undoped thick epi films that provide the benefit. They enable higher voltages with larger R(off)values, and contribute to higher switching speeds and reduced device footprints (see figure 1).

For MEMS devices—gyroscopes, pressure sensors, digital compasses, accelerometers, and now micromirrors for a new breed of pico projectors—thick epi opens a route to lower cost manufacturing, combined with greater device sensitivity and performance thanks to the taller

mechanical structures (i.e., the smaller footprint) it enables (see figure 2).

Additionally, manufacturers who have been purchasing device-layer silicon-on-insulator (SOI) wafers now have the option to produce high-quality thick epi films themselves, thereby reducing wafer costs.

Figure 1. Power devices such as superjunction MOSFETs, illustrated above, can benefit from thick epi layers. In (a) we see the predominant manufacturing method, where a thick epi deposition is doped in one area, repeated several times to build thickness, and then is annealed. In contrast to this multistep method, (b) shows a simpler approach where a thick epi layer is grown, etched using deep reactive ion etch (DRIE), and then filled using a doped thick epi capability to build a superjunction power MOSFET. R&D implementations of this are shown in (c) and (d), as companies continue to experiment with thick epi, DRIE, oxide fill and other processes.

Figure 2. New MEMS devices such as micromirrors for pico projectors, along with established MEMS products such as gyroscopes and accelerometers, can leverage thicker silicon device layers for improved performance and benefit further from still thicker layers. The images shown are scanning electron microscope (SEM) photographs of a MEMS gyroscope (top) and stand-alone micromirror.


Applied Materials is committed to ongoing investments and R&D activities to support emerging applications for 200mm technology. This includes continued development of its widely used 200mm Centura Epi platform.

Given the potential benefits of uniform, high-quality thick epi layers, Applied Materials has developed a unique hardware upgrade kit to enhance the thick silicon epi film capabilities of the 200mm Centura Epi platform. The upgrade kit enables users to deposit silicon epi up to 100μm thick with outstanding film properties, uniformity, lower defect levels and throughput, in the same chamber where they currently grow thin epi layers. Development is ongoing to further enhance the growth rate for higher production throughput and for final thickness, currently targeted at 150μm.

This single-chamber, single-vendor capability is unique in the industry, and helps users reduce costs and complexity. It is available now on new and refurbished 200mm Centura Epi tools, and as an upgrade for the installed base. It is one more way in which Applied—a pioneer in epitaxial technologies and the leading supplier of epitaxial deposition equipment—helps customers extend the life cycle and maximize the value of this familiar, reliable and cost-effective toolset.

The new kit is based on hardware upgrades, including an advanced motorized lift, a new tapered susceptor design, a new susceptor alignment tool (SAT) and other hardware and software enhancements transposed from advanced Applied 300mm toolsets. It provides the capability to grow thin (<1μm) or thick (≤ 100μm) silicon epi layers in the same process chamber, enabling higher growth rates (up to 6μm/min), greater process flexibility, and the ability to produce a higher number of better performing devices.


Thick epi is currently being used to enhance insulated gate bipolar transistors (IGBTs) and superjunction (SJ) MOSFETs. Higher density devices can be built using these thicker epitaxial silicon layers. This enables IGBTs to operate at higher power levels and SJ MOSFETs to switch faster and at ever higher voltages while maintaining small form factors (see figure 3).

Figure 3. SJ MOSFETS are still a small part of the overall power semiconductor market (~10%) but their growing voltage- and current-handling capabilities, combined with their existing high switching-speed capabilities, will eventually threaten the market share of iGBTs. (Figure courtesy of Yole Développement.)

SJ MOSFETs are a newer device-type gaining preference over conventional power MOSFETs in applications where small size and fast switching at high voltages are key requirements. These include power adapters, game consoles, solar inverters, and battery chargers for products such as tablets and laptops.

Conventional planar MOSFETs have cells built from well-like structures, whereas the body of an SJ MOSFET features cells with a columnar structure in which p-type columns extend vertically through a relatively thicker n-doped epitaxial region to the substrate (see figure 4). Conventional power MOSFETs suffer from a so-called “silicon limitation” where an increase in the voltage-blocking capability causes an increase in on-resistance, making it more difficult to achieve energy savings in the end product.

With SJ MOSFETs, however, the relatively thicker and highly doped epi region enables higher breakdown voltages, while the close spacing of tall, thin columns increases cell density and allows voltage- and current-handling capabilities to be maintained as die sizes shrink. Reduced on-resistance is achieved by reducing the overall thickness of the die.

Figure 4. Conventional planar MOSFET structure at left, and SJ MOSFET structure at right. SJ MOSFETs have cells with p-type columns extending vertically through an n-doped epitaxial region to the substrate. The thicker p-doped region enables a lower R(on), as well as a higher R(off) in the locking state.

To build these devices, figure 1 (b)–(d) shows how the thick silicon epitaxial layer is subsequently etched using a dedicated DRIE tool to form trench structures. The trenches are then backfilled with highly doped void-free material using a reduced-pressure (RP) epi process, also enabled by the 200mm Centura Epi platform. Using its own 200mm DRIE tools, Applied Materials has demonstrated aspect ratios for these trenches as high as 40:1, with critical dimensions of about one micron in trenches 44μm deep.

Key requirements for the overall process include an atmospheric (ATM) epi process to grow the thick n-type layer silicon, followed by a DRIE step that demonstrates precise control over sidewall profile and trench top and bottom critical dimensions. That in turn is followed by an RP epi process for fast, void-free filling. The Applied 200mm 3-chamber Epi Centura platform can accommodate both ATM and RP configured chamber-types.


The push for more functionality in portable electronics has resulted in more MEMS content in each new generation of consumer devices to support features such as gesture recognition and GPS.

As with integrated circuits, MEMS components are facing constant downward price pressure. There is also simultaneous demand for greater performance and smaller sizes because of the importance of form factor in handheld systems.

Thick epi opens up the possibility for lower-cost manufacturing, and because taller, thinner mechanical structures can be fabricated from thicker epi layers, the sensitivity and performance of these tiny machines can be increased while their overall sizes are kept to a minimum (see figure 5).

Figure 5. Thicker epi layers combined with an advanced DRIE etch process can enable higher structural density and thus higher sensitivity in MEMS devices (and in just about any type of electrostatic device that utilizes arrays of interdigitated comb-finger structures for either sensing or actuation). As shown in the above illustration and accompanying equation, device thickness (t) is directly proportional to force and voltage applied. Increasing (t) in the device design provides the opportunity to either reduce V, or to keep everything constant and achieve a greater F (e.g., capacitive sensitivity), depending on the device’s function.

A key requirement is that the total thickness variation (TTV) of the device layer be exactly the same across the entire wafer. This need arises because many types of MEMS devices are operated at their mechanical resonance, or natural, frequency. This is the frequency at which their sensitivity, or displacement for a given input energy, is maximized.

The resonance frequency is normally the device’s operating frequency, and any variation in the thickness of the device layer will trigger a change in it. That could inadvertently lead to MEMS devices with differing performance characteristics produced on the same wafer (see figure 6).

Such variations in operating frequencies may result in devices that operate outside the range of their control circuitry. Or conversely, more expensive control solutions would be required to accommodate the range in mechanical device frequencies. An ideal scenario would be where a high level of repeatability is achieved for the manufacture of the MEMS device such that a moderate-to-low cost application-specific IC can be employed to control it.

In contrast to other approaches, the enhanced 200mm Centura Epi platform enables greater within-wafer uniformity and repeatability for both thin and thick epitaxial silicon layers. Using Applied’s Epi Uniformity and Repeatability Kit, manufacturers can improve TTV for epitaxial silicon films by as much as 30%.

The process kit, developed specifically for thick epitaxial silicon, includes a motorized wafer lifter to ensure accurate wafer placement; a newly designed tapered susceptor plate that benefits thin and thick films by eliminating wafer movement and avoids “wafer bridging” issues commonly seen when growing very thick epi films; and finally a new susceptor leveling tool that ensures repeated and accurate wafer positioning during post-chamber cleans.

These and other technologies help users achieve superior on-wafer performance and higher productivity versus other commercially available epi tools.

Figure 6. For resonant MEMS devices, the TTV of the device layer must be minimized across the entire wafer, given the large effect it has on the fundamental resonant, or natural, frequency of the MEMS devices produced on that wafer. The figure above mathematically illustrates how changing the physical dimensions of a structure—for example, by excessive variations in thickness—would lead to changes in resonant frequency.


At present, device-layer SOI wafers are fabricated using a complex, multistep process. First, a silicon wafer is wafer-bonded directly to a handle wafer with an oxide layer (either thermally grown or fabricated via CVD). The silicon is ground down to a specified thickness, planarized via CMP, and then transferred to an insulating substrate, after which devices can be built with it.

Applied’s enhanced 200mm Centura Epi platform offers a simpler approach. An insulating substrate is grown or deposited directly on a handle wafer. Then, a uniformly thick epitaxial polysilicon layer is grown directly on top of it (see figure 7).

Figure 7. Two methods of fabricating device-layer SOI wafers. The left diagram shows a thick epitaxial growth approach, while at right a more complicated wafer-bonding/grinding/polishing approach is illustrated.


As with any new technology, the fabrication of thick epi films brings challenges as well as opportunities. The major challenges are:

  • Uniformity: it’s more difficult to achieve overall film thickness and doping uniformity with thicker epi films because the thicker the film, the more difficult it is to control doping concentration across the wafer and through the thickness of the film. A constant and uniform wafer temperature is also critical.
  • Film growth rate: keeping a tool’s productivity high is always a key goal; Applied’s current growth rate target is to achieve deposition rates of ≥6μm/minute per chamber for single-step film deposition.
  • Wafer bridging: bridging, or sticking, has always been a concern when growing films thicker than 20μm in any epi reactor.
  • Film quality and potential chamber coating: higher growth rates and longer process times may promote film defects and chamber dome coating.
  • Repeatable wafer placement: after a chamber clean, susceptor leveling can affect wafer placement, which could decrease device performance and yield.


With more than 800 chambers installed worldwide, Applied Materials’ 200mm Centura Epi platform is well suited to help customers address these challenges. Summaries of the enhanced Centura performance in fabricating a 100μm-thick epi layer are shown in figures 8 and 9.

Figure 8. The two charts show thickness (left) and resistivity (right) results for a 100μm-thick epitaxial silicon film grown across a 200mm wafer at a rate in excess of 5.9μm/min with Applied Materials’ enhanced 200mm Centura platform. The thickness nonuniformity and resistivity nonuniformity are both < 1%.

Figure 9. The chart shows excellent on-wafer particle performance for the same 100μm-thick epitaxial silicon film described in the previous figure.There were less than 20 particles (adders) >0.12μm across the 200mm wafer.

Developments such as thick epi films on cost-effective 200mm tools will help bring about enhancements in the power semiconductors and MEM devices that are the prerequisites for today’s fastest-growing electronics applications. Applied Materials is working with device-level partners in the automotive and consumer markets on next-generation devices that employ thick epi, and is continuously optimizing process and tool development to extend thick epi capabilities further.

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