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Endura® PVD 200mm

Today’s 200mm Physical Vapor Deposition (PVD) challenges focus on the ability to deposit thicker, highly uniform, low temperature compatible films. In the power device market, devices with reduced form-factor and footprint that are capable of switching at high speeds are driving the requirement for advanced heat dissipation technologies such as Al layers in the thickness range of 4µm to over 100µm.

Emerging applications in micro-electro-mechanical systems (MEMS), CMOS image sensors and packaging technologies such as through-silicon vias (TSV) are driving PVD development on films like Aluminum Nitride (AlN), Indium Tin Oxide (ITO), Aluminum Oxide (Al2O3) and Germanium (Ge).

Endura PVD 200mm

The Applied Endura platform is the most successful metallization system in the history of the semiconductor industry. With deposition capabilities spanning front end metallization like cobalt and tungsten, aluminum and copper interconnect, as well as packing applications like under bump metallization, a vast majority of microchips made in the last 20 years have been created using one of the over 4,500 Endura systems that have shipped across the globe.

The Endura’s ability to deposit a wide variety of ultra-pure films with tight control over film thickness, superior bottom coverage and high conformality are key to the fabrication of leading edge devices.

The capacity for up to nine process chambers provides the system the ability to mix and match chambers to create integrated multi-step process sequences. The highly configurable Endura platform supports two preclean chambers for native oxides removal, up to six PVD chambers, and the option for two MOCVD chambers to ensure customer film deposition and device performance requirements are met.


With thousands of Endura’s still in production, with many in their original configuration, there are a number of product improvements available which provide improved process performance and tool productivity. For example, throughput bottlenecks at the Cool Down chamber can be eliminated by conversion of Chamber A from Pass Thru to Cool Down. Wafer placement errors can be eliminated with EZ LCF while improving the performance for clamped processes with tight edge exclusions and eliminates stack-up errors related to multi-chamber process sequences. In addition, chamber upgrades are available for many of the chambers, including TxZ, to improve on-wafer uniformity and reduce maintenance.