Patterning has enabled many generations of 2D scaling. In the past, patterning relied on a series of relatively straightforward optical masks and photolithography steps to print patterns, guiding subsequent materials removal and deposition steps. More recently, advances in photolithography have not kept pace with advances in chip design.
Even as the next EUV generation of lithography enters the roadmap, chipmakers are taking advantage of cost-effective, self-aligned multipatterning techniques, using pitch multiplication to create two or four lines from a single lithography pass. With or without EUV, edge placement error is a challenge that chipmakers must overcome to correctly align the features in one layer with the complementary features in the next. Materials engineering can play an enabling role, offering wider landing zones that can tolerate alignment variances that would otherwise adversely impact yields.
As the cost of lithography has increased, memory designers have taken to building 3D devices whereby cost reductions come not from 2D bit scaling, but 3D bit stacking. Costs are reduced by increasing bits per cubic millimeter instead of bits per square millimeter.