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New FabVantage Service Improves Equipment Performance

By Roman Mostovoy, PhD

As devices become smaller and more densely packed, and the complexity of integrated circuits grows, defect reduction becomes more challenging while remaining critical to chipmakers’ competitiveness. Foundry, memory and logic fabs require a method, skills, and specialized tools to effectively reduce defect levels with minimal disruption to production. A new defect-reduction service from the Applied Materials FabVantage™ Consulting team offers a specialized methodology, process expertise, data analytic techniques, and diagnostic instruments that streamline identification of root causes.

Minimizing the number of defects on production wafers is critical for fab productivity and competitiveness. Understanding the defect-reduction process is essential for successful implementation and validation of corrective measures. To achieve the single-digit defect counts required at the 14nm technology node and below, manufacturers must take a structured approach to root-cause detection and correction that leverages a defect knowledge base, broad equipment design and process expertise, and proven best-known methods (BKMs), in addition to state-of-the-art metrology, inspection, and analysis.

Defect reduction is not a "one size fits all" undertaking. Numerous factors can contribute, including hardware configuration and parts cleanliness, process sequence and parameter settings, operation and maintenance procedures, calibration, and system software. These factors can affect the same process running in different fabs to differing degrees. The differences create fab-specific defect populations that may be similar with respect to the type(s) of defect, but derive from different—sometimes multiple—root causes. For example, failure modes responsible for defect excursion events may not be the same as the root causes of the primary defects present on every wafer. As a result, diagnosing the original source of defect or excursion creation can be a time- and labor-consuming combination of preventive maintenance (PM) work, parts replacement, hardware calibration, and recipe tuning that disrupts production for several days.

Defect-Reduction Methodology

Given that each defect scenario is unique, expeditious discovery of the root cause depends on a structured approach that applies the same set of steps to each investigation (see figure 1). The Applied Materials FabVantage Consulting team, in collaboration with Applied's process groups and field support personnel, has developed a defect-reduction methodology that has been effectively used to improve baseline performance, reduce the rate of defect out-of-control (OOC) events, shorten PM green-to-green time, and extend mean time between cleans (MTBC).

Figure 1. Methodical determination of defects and root causes is an essential first step in defining corrective actions.

Typically, skilled engineers perform initial benchmarking of current system performance on blanket monitor wafers (baseline) within a FabVantage 360™ evaluation (see figure 2). The benchmark measures a tool’s performance on several metrics and compares it to BKMs and best in class. The assessment gives a holistic view of performance gaps and enables prioritization of solutions and quantification of benefits. The unit process aspect of the assessment scores recipes, particle performance, and implementation of fault detection and classification; these data become the basis of the assessment step shown in figure 2. The monitor wafers are run regularly over a period of several weeks so that time-variant defect mechanisms can be captured. Because they are often run as part of standard fab procedure, collecting this data does not appreciably detract from the process tool’s normal uptime.

Figure 2. The assessment step in the Applied FabVantage approach to defect reduction identifies root cause(s); customers can then elect for the team to implement corrective actions and maintain improved tool performance.

FabVantage specialists use conventional and specialized instrumentation to obtain defect adder counts and their pattern on wafers. These data sets are then charted against wafer counts and key events, which in turn aids development of a Pareto chart illustrating the relative contribution of specific factors that generate defects (see figure 3).

Figure 3. Facility conditions, equipment, materials, and cleanliness of parts contribute the most to the high defect level of the tool’s baseline performance.

If the defect Pareto shows PM to be a significant contributor, PM diagnostics are performed using specialized instruments. Several chambers in the fab are inspected to determine particle densities on key chamber components and incoming parts, validate wet clean procedure compliance with Applied’s BKM, gather key PM-related system constants, and validate robot calibrations. In addition, hardware troubleshooting is conducted if evidence of hardware malfunction is observed. The manufacturing processes being run are also diagnosed if the Pareto points to them as a major contributory factor.

Once the tool-specific defect Pareto has been generated for baseline operating performance, the FabVantage team creates a project-specific "roadmap" for improvement (see figure 4). Defects are first classified into types by location, size, appearance, and composition. Then each defect type is analyzed using a combination of inspection and analysis technologies; team members’ thorough knowledge and experience of the tool and the type of process being run; customer-specific factors; and experiments designed to evaluate the defect contributions from different sources. Identification of root cause is the product of all these factors.

Figure 4. As shown in this example, the defect-reduction "roadmap" addresses defects systematically in order of contribution to overall counts. (Source: Applied Materials, Inc.)

Once the root causes of the most significant contributors to the tool’s defect Pareto have been identified, the FabVantage team proposes an implementation plan to address them. If the fab agrees to the plan, corrective measures may involve improvements to hardware, process, PM, or some combination of these. The effectiveness of the corrective measures is validated by a confirmation run in which data is collected in the same manner as for the initial baseline assessment and reviewed to ensure that the goals of the implementation plan have been achieved. The result establishes a new defect Pareto corresponding to the improved performance and becomes the new production baseline as well as the roadmap for future defect reduction. Following validation by the confirmation run, the same corrective measures are implemented on all affected tools in the fab. If the fab owner desires, their operation can be monitored by FabVantage team members on an ongoing basis.

Demonstrated Effectiveness

The above methodology has been used and validated in a variety of scenarios, some of which we highlight here.

Reducing Particle Counts

In one case, the defect Pareto generated from the tool baseline indicated that the tool itself was a major source of particles found on both sides of the wafers. Investigative images, metrology, and tool operation experiments revealed that the root cause was the materials used in the wafer transfer/handling equipment. They generated high defect counts in the following ways:

  • As wafers came in contact with rough surfaces on the equipment over an extended period of time, the surfaces degraded, creating particles that acted as abrasives and generated even more particles.
  • Equipment material was so hard or adhered to the wafer so strongly that scratching occurred on the back side of the wafers.
  • Electrically non-conductive materials were becoming charged and, being unable to dissipate the charge, were causing an electrostatic attraction/repulsion effect that in turn generated additional charged particles.
  • Particle-producing wafer slippage was occurring because friction was not optimized.

Defect reduction therefore involved replacing the materials used in the affected parts of the tool. Smoother, electrically conductive materials with hardness less than that of silicon and low-adhesion/high-friction properties were used in new robot blades, lift pins, the pedestal, and lift fingers. Figure 5 shows the improvement in performance achieved through these hardware upgrades.

Figure 5. Defect performance improves significantly after hardware upgrades are implemented. (Source: Applied Materials, Inc.)

Improving Uptime

Another case addressed an increase of in-film defects over time, which shortened chamber MTBC and reduced tool uptime. Baselining the tool’s performance, the in-film monitor defect Pareto highlighted Si/O and Si/O/Al/F as the predominant defects of concern. Detailed inspection and failure analysis of components for one of the gas lines on multiple chambers revealed that these defects were accumulating on the gas line’s orifice and feedthrough, likely owing to the backflow of source radicals of AlF or O species during chamber cleaning. Also, source radicals could be reacting with residual moisture to generate O or ozone radicals, and resulting conglomerates of SiO particles.

Here the issue was remedied by modifying the process recipe. First, the back-diffusion of radicals to the gas line in question was mitigated by flowing helium through the line during cleaning and also by maintaining positive helium flow through that line during all reactant gas introductions and transients. Second, an extended purge of inert gas was implemented to eliminate outgassing from the process chamber at low pressure. Two extended runs were completed to evaluate the performance of the defect-reduction measures:

a 2000-wafer run with baseline conditions and a 4000-wafer run with the new recipe. The latter suppressed mainframe exposure to outgassing and improved defect performance (see figures 6 and 7).

Figure 6. Comparison of defect Paretos before and after implementing defect reduction shows a 10-fold and 2-fold improvement in Si/O/Al/F and Si/O defects, respectively. (Source: Applied Materials, Inc.)

Figure 7. Comparison of in-film defect counts before and after implementing defect reduction. (Source: Applied Materials, Inc.)

Increasing Mean Wafers Between Cleans

Yet another situation involved use of cleanliness control metrology to reduce defect counts and improve uptime and mean wafers between cleans. Insufficient cleaning often results in production delays while the process chamber is put through multiple cleaning/pumping cycles to pass defect qualifications. Here, the baseline performance Pareto pointed to the remote plasma source as one of the subsystems contributing significantly to wafer defects. Consequently, attention focused on evaluating defect performance on remote plasma source parts received from different cleaning suppliers.

A complementary evaluation of different cleaning solvents for chambers and mainframes revealed that wipes wetted with deionized water (DI) and a mix of DI/isopropyl alcohol were equally effective in producing a 10-fold reduction in surface particles from ~ 2,500def/inch2 to ~ 250def/inch2. However, following this step by a second wipedown using another specialized solvent improved cleanliness even more (< 50 def/inch2), as shown in Figure 8. This 2-step procedure cut PM and post-PM recovery time by more than half, from 48 hours to 20 hours, helping improve productivity through increased tool availability.

Figure 8. Surface particle detector results before and after process chamber cleaning. (Source: Applied Materials, Inc.)


The Applied Materials FabVantage Consulting team has developed and successfully demonstrated a defect-reduction methodology that applies a structured approach enabling corrective measures to be implemented rapidly. Customers can then elect to have the team continue to monitor production tools to maintain the improved level of performance. This methodical approach to defect reduction expedites ramping by reducing downtime and enhancing fab yield and output.

The author extends appreciation to Suketu Parikh for his assistance.

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