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The Last Word

IBM Microelectronics: The Next Chapter

David Lammers

“We’ve got to reinvent ourselves, like in prior generations.”

IBM CEO Ginni Rometty, announcing IBM’s transfer of its semiconductor operation to GLOBALFOUNDRIES.

At the 2014 International Electron Devices Meeting (IEDM) in mid-December, IBM and Intel engineers will face off with competing views of FinFETs at the 14nm node, using silicon-on-insulator and bulk silicon approaches, respectively. Those two “late papers” in San Francisco may be the last time that engineers from these companies go head-to-head, the final scene of an intense technology competition.

But don’t be too sure. IBM will keep its hand in the industry, sharing the results of its work with GLOBALFOUNDRIES through their collaboration at SUNY Polytechnic and spending $3 billion over the next five years on semiconductor-related research. That, plus the likely transfer of many IBM semiconductor staff to GLOBALFOUNDRIES, would suggest that the competition will continue.

Go back 30 years, to the days when IBM engineers such as Bernie Meyerson, Gary Patton, and Hans Stork were touting the benefits of silicon-germanium-channel ICs, mainly for high-speed telecom applications. It was the beginning of a very healthy SiGe IC business for IBM’s Essex Junction, Vermont, fab, burnishing a tradition of innovative excellence that included the single-transistor DRAM and the all solid-state mainframe.

As Intel rode the microprocessor to greatness (in the IBM PC initially), IBM and Intel began a series of historic technology competitions. IBM promoted reduced instruction set computing (RISC) architectures, while Intel threw down the gauntlet and said its CISC-based processors were just as fast.

Then IBM got serious about silicon-on-insulator (SOI), a great technology if the cost of the SOI wafer agrees with the business model. In the summer of 1997, Bijan Davari, then the head of IBM’s microelectronics division—and a pioneer in the adoption of chemical mechanical planarization(CMP) early in his career—announced that IBM would use SOI in its processors.

For Intel and its MPUs, SOI didn’t compute. Intel’s Mark Bohr argued that bulk silicon was as fast and as low-power as SOI, and cheaper to boot. IBM accomplished a brilliant rebuttal by building an embedded DRAM (eDRAM) using the insulating layer in the SOI substrate. To my knowledge, Intel has never used embedded DRAM. (Later, IBM would argue that it got such a big boost from putting on-chip eDRAM in its Power processors that it didn’t need to move to high-k as early as Intel.)

When it came to copper interconnects, IBM was first to the table. It was after a keynote speech at SEMICON Japan in early December 1997 that Bohr was asked about rumors that IBM would give a ground-breaking paper on copper interconnects at the IEDM meeting scheduled for later that same month. Bohr answered by saying that copper interconnects were a good technology, but that for Intel it could stay on its performance roadmap with aluminum wires for another generation, while enjoying lower manufacturing costs and higher yields. Sure enough, at the 1997 IEDM in Washington, D.C., Dan Edelstein presented IBM’s plan for copper interconnects. Wall Street took notice, with IBM’s stock price taking a big jump after the Wall Street Journal headlined IBM’s copper advance.

I first heard about strained silicon during a busy day of briefings at East Fishkill, New York. Strained silicon? What is that? Reporters got a short whiff of an answer about the kinds of performance gains that could be had by putting a layer of germanium atoms underneath the active silicon. Intel pulled a jujitsu move on everyone, figuring out how to strain the pFET channel with locally deposited germanium next to the channel. Intel got a big jump on the rest of the industry—including IBM.

These technology competitions regarding SOI, copper, and strained silicon were precursors to the Big Kahuna: high-k dielectrics. Intel again innovated, figuring out how to do a gate-last or replacement-gate approach. Intel got to high-k well before anyone, despite an all-out effort by IBM, which had chosen to go down the gate-first approach. The billions that went into high-k dielectric developments by both companies represented, to my mind, the most intense technology competition in the history of the semiconductor industry.

Now, here we are. IBM’s essentially gone fabless—but is definitely not gone from the race for advanced semiconductor technology development. And its decision to tie its chip manufacturing to GLOBALFOUNDRIES strengthens that company’s resolve to be a leading-edge player in the foundry business. As we close the chapter on IBM as a device manufacturer, we can’t wait to turn the page and see what’s next for this respected industry innovator.

Gary Patton,
VP, Semiconductor Research & Development Center at IBM

Mark Bohr,
Intel Senior Fellow

David Lammers is an Austin-based technology journalist.