skip to main content

METHODOLOGY FEATURE: Partnering With Customers to Improve Yield

by Suketu Parikh and Patrick Fernandez

Chip design and fabrication is becoming highly complex; potential sources of yield loss are multiplying and are often obscure. This makes rapid, problem-free production ramping increasingly challenging in a fast-changing market where time is at a premium. Fabs repurposing older systems find it especially difficult to achieve desired yields, because the tools have not been optimized to meet the more stringent specifications of the new technology node. Combining the top-down resolution process typically used in fabs with the equipment manufacturer’s bottom-up optimization can streamline defect resolution and shorten the time to ramp.

Shrinking feature dimensions; growing complexity of device architectures; interactions among new materials; and variabilities among lots, chambers, and tools are among the factors posing significant challenges in ramping advanced ICs to production-volume yield in today’s fabs. Figure 1 illustrates the typical ramp experience as compared to the smooth, efficient progress that fab operators desire. Yet even as it becomes more arduous to ramp, the imperative to accelerate it grows as shorter product lives and narrower market windows compress the time over which a new technology can generate top dollar for the producer.

Figure 1

Figure 1. Ramping to production is typically an arduous process.

The pressure to expedite ramping is especially demanding when systems are being repurposed from an earlier technology generation to a more advanced one. Generally, fabs reuse approximately 80% of their older systems. Not only must these tools be optimized to meet the specific requirements of a new process, they must be comprehensively rebaselined to a higher standard of operation.

In addition, matching performance between qualification wafers and product wafers poses a significant challenge given such factors as interactions from previous steps, topography, pattern density, and edge defects.

Expediting the yield ramp takes a partnership between the chipmaker and the equipment manufacturer. This partnership combines the chipmaker’s top-down approach to defect resolution with the manufacturer’s bottom-up method of examining hardware, process, integration, and environment to streamline root cause identification of specific defects. In this way, the full spectrum of factors affecting yield (see figure 2) can be systematically and addressed.

Figure 2

Figure 2. Numerous factors affect yield in the manufacturing of today’s devices.

Chipmaker's Top-Down Defect Resolution

Chip manufacture at today’s most advanced sub-40nm nodes is significantly more demanding than at previous generations. The challenges stem from the introduction of new materials, new device and integration considerations, tighter process margins, and process interactions, all of which affect yield. Figure 3, illustrating high-k metal gate technology, shows the many factors affecting yield. Process interactions, arising primarily from the greater number of fabrication steps; gap-fill, planarization, and patterning challenges; and film interactions create more stringent requirements for equipment and process to function precisely. These in turn necessitate intricate FDC sensor excursion control and chamber-performance matching as discussed later.

Figure 3

Figure 3. Complex process integrations, such as high-k metal gate, increase the potential for a wide array of yield-limiting defects.

Conventional yield loss analysis in the fab employs a topdown analysis of defect issues based on Fail Pareto charts of finished wafer lots. Table 1 lists key contributors to yield loss for a typical 28nm logic process flow that could appear in a Pareto chart. Many of these derive from multiple sources. Effective, permanent resolution of each issue requires understanding of all potential causes and holistic remediation. The right side of the table shows that correcting some issues will require complete investigation of hardware, process, FDC sensors, and integration.

The conventional Fail Pareto approach to yield improvement implements failure analysis and root cause determination for each defect type appearing on the chart through an iterative approach that first examines process integration, then the unit process, and lastly hardware to determine and remedy the source of the defect. This method is effective only if resolution of the defect is permanent and the Pareto remains stable over successive process qualifications. If the analysis has not considered all the factors potentially contributing to the defect issue, the problem is only partially fixed and is likely to reappear. In addition, successive Paretos will often exhibit variation in rankings or types of defects as the result of day-to-day in-line variation caused by mismatched chambers, process variability or excursions, unanticipated process interactions, or random malfunctions. This instability makes identifying the true root cause of a given defect more difficult and time-consuming.

The Applied Materials FabVantage consulting group implements a unique approach in complementing the chipmaker’s top-down approach with a bottom-up approach to expedite yield ramping through optimal tool baselining and process-specific optimization.

Table 1

Table 1. Type and potential origin(s) of top yield losses in high-k metal gate fabrication.

Equipment Manufacturers' Bottom-Up Defect Resolution

The bottom-up approach reverses the sequence of investigation in resolving yield-limiting defects. Once the top issues, and module-level and process-related performance targets are known for a specific new technology introduction, the bottom-up approach first identifies and eliminates fundamental hardware and baseline-process deficiencies to establish a “golden tool.” It progresses from there to unit process optimization, and finally to integration optimization. While these procedures are straightforward when a new product is brought online at the technology node for which it was designed, they can be more challenging when working to enhance operation of repurposed tools.

Establishing the golden tool involves detailed audits of the hardware, process, facility, and procedures used in periodic maintenance. Hardware audits include chamber inspections and system health checks to identify issues, such as mainframe particles, resulting from inadequate cleaning, back-side scratching, wafer slippage, heater pad wearout, and MFC bursts that create particle excursions. With the equipment manufacturer’s perspective, the FabVantage team is also sensitive to defect-generating mechanisms that can arise over time (e.g., wear and tear on moving parts and process side effects on chamber surfaces), and to the condition of moving parts over successive maintenance sessions. Further, the team can initiate tool upgrades to reduce defect count and tighten process performance.

A key step in the bottom-up approach is to establish stable, optimal baseline process performance. This is done through a process audit that investigates key process steps, gas flow, plasma terminations, plasma treatments, chamber cleaning, chamber conditioning, and interactions between a given process step and those immediately preceding and following. In addition, process signatures that cause withinwafer variation (e.g., center/edge or asymmetric) are examined and remedied as are wafer-to-wafer variations caused by differences in the service lives of the chamber, other hardware, or consumables. E3/FDC sensor trace analysis follows for priority sensors and critical steps to verify that tools replicate a predefined golden trace. Finally, sensor excursion models are developed based on individual tool performance and overall in-line defects; these are then used for ongoing monitoring of the optimized tool/process and detection of subsequent excursions.

This detailed bottom-up analysis optimizes the “health” foundation of the tool, eliminating hardware and basic process-related factors as potential root causes of defects. In other words, it reduces the “noise” level, making it easier to identify the “signal” that is the real culprit in a given situation. Once the golden tool is established, the same improvements are fanned out to the rest of the fab for yield ramp.

In the case of process modules, stabilizing yield distribution and narrowing variations from process excursions involves more than examination of each unit system and process. Capabilities of the integrated tool set must be verified and results from blanket wafers must be seen to translate correctly to product wafers on which pattern densities and other topographical challenges might alter performance. Also, electrical parameters of the completed module must meet criteria across individual wafers, between wafers, and between chambers.

Partnership Benefits

The FabVantage team’s approach of partnering with chipmakers in improving ramp yield offers two major benefits.

First, detailed knowledge of the hardware and its behavior across multiple systems and chemistry variations equips FabVantage consultants with lessons learned and insights related to possible sources and root causes of yield-limiting defects. This knowledge complements the chipmaker’s expertise in the unique aspects of his process and can amplify top-down yield improvement.

Second and more importantly, the combination of customer data on yield Pareto and equipment maker data on tool performance provides a critically more comprehensive data set that enables efficient root cause analysis and correction of the true root cause.

The clearer picture obtained through the combined top-down and bottom-up approach (see table 2) minimizes repeated “fire drills” that can cause significant delay in ramping when root causes of defects are obscured by higher baseline defect levels and excursions that can vary randomly from run to run. Instead, yield improvement becomes an efficient, systematic process.

Table 2

Table 2. Comparison of conventional top-down and FabVantage team approaches to yield improvement.

Once golden tools have been set up, ensuring consistent performance across the fab when fanning out the process or module can present a further challenge. Process results may match on blanket wafers but vary on product wafers. Here again, FabVantage team knowledge can facilitate a resolution. Comprehensive understanding of system constants, calibration targets, system sensors, and which of them can modulate process drift and excursion or specific onwafer parameters can effectively complement the chipmaker’s familiarity with process behavior to pinpoint the most appropriate path of investigation.

FabVantage consulting engagements have achieved successful results at several major advanced technology customers, expediting yield improvement by reducing variation in process performance and defect excursions through systematic hardware, process, and integration audits and remediation. These successes are founded on yield-improvement collaborations by FabVantage consultants and technologists at the Applied Materials Maydan Technology Center (MTC).

The following example of this collaboration is characteristic of the FabVantage team’s approach at customer sites. Figure 4 illustrates issues related to BEOL defectivity. In this case, post-CMP patterning defectivity was causing yield loss. The FabVantage/MTC team suspected that the defectivity resulted not only from CMP, but from multiple preceding processes and the relative stability of each process (i.e., low-k dielectric stack deposition, damascene patterning [lithography and etch]) interacting with incoming topography and defects. Besides overall planarity, the cumulative effect of defects from the most recent layer and copper wiring defects from previous layers (i.e., missing metal, scratches, and slurry residue) could have a significant impact on patterning defects in the next layer to be processed

Figure 4

Figure 4. Defectivity in successive layers, accumulated through the processes sequence, can obscure the true root cause of a defective top layer.

The team’s failure analysis proceeded as follows:

  1. Defect classified as metal line lithography open (having multiple potential causes and exhibiting high variability from wafer to wafer).
  2. Cause identified as resist scumming.
  3. Root cause identified as topographical variation (possibly local defects).
  4. Solution path determined: identify critical hardware and processes; identify base defectivity/excursion rate and reduce systematically by detailed hardware inspection; corrective action/maintenance; and resolution of apparent process issues.
  5. Identify short-loop tests for undesirable process interactions and address variability in defectivity of dielectric stack, patterning, and copper wiring.
  6. Systematically reduce excursions in defect count by eliminating unit process excursions and setting up sensor models to establish process control limits for monitoring and reducing future excursions (see figure 5).
  7. Improve scumming, identify multiple causes of stack defects.
Figure 5

Figure 5. Representative sensor model for monitoring defect excursion.

By comparison, the conventional top-down approach would have started with the yield and lithography teams collaborating to improve planarization and the depth-of-field window. The variability of the incoming damascene stack and its underlayer would further complicate overall improvement as planarization process adjustments would impact the patterning window without eliminating the root cause of the defects.

Using the same kind of analytical sequence as detailed above, the FabVantage team has helped numerous customers systematically address hardware and process issues at the root of defects in copper wiring layers and the CVD stack. They have also extended the lithography depth of focus window by improving within-wafer planarization uniformity. This methodical approach has resulted in systematic reduction in each defect type observed by these customers, producing overall improvement in multi-layer BEOL yield, such as that illustrated in figure 6 from the collaboration with MTC.

Figure 6

Figure 6. Systematic reduction in BEOL module defectivity achieved on in-house wafers.


Ramping to production-volume yield in the shortest time possible is challenging for today’s fabs, particularly when older tools are being repurposed for a more advanced technology node. Fabs can save significant time and cost by implementing a ramp yield-improvement partnership with their equipment manufacturer. The chipmaker brings to the partnership its top-down analysis approach and in-depth expertise in its processes. The FabVantage team brings systematic bottom-up auditing of potential sources of yield-limiting defects; broad problem-resolution expertise; and proven methodologies for yield loss analysis and remediation, enhancing baseline tool performance, and minimizing process variability and excursions. Working together, they eliminate the “fire drills” and delays commonly experienced, replacing them with a smooth progression from one golden tool to fab-wide fan out and achieving sustained production-volume yield with fewer preproduction runs.

Acknowledgements: The author thanks Patrick Fernandez, head of FabVantage Yield Practice, for his guidance, and Jeannette Hoffman for editorial assistance; also Mehul Naik (BEOL Integration MTC), Helen Armer, and the FabVantage yield practice team for their support.

For information contact